1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same and, more particularly, to a dynamic semiconductor memory device suitable as the secondary cache memory of a microprocessor and a method of manufacturing the same.
2. Description of the Prior Art
Conventionally, the secondary cache memory of a microprocessor is formed from an off-chip type synchronous SRAM (Static Random Access Memory). The secondary cache interface of the microprocessor is generally designed on the assumption of the off-chip type synchronous SRAM.
With the development of micropatterning techniques, demands have arisen for embedding a secondary cache memory and a microprocessor on one chip.
To form a secondary cache memory on a chip, a DRAM (Dynamic Random Access Memory) small in memory size must be used to increase the memory capacity and improve the total performance of a microprocessor including the secondary cache memory.
A DRAM/logic embedding process of simultaneously manufacturing a DRAM and other logic circuits has already been practically available. If layout data of a conventional microprocessor is directly used as a macro, and a DRAM macro conforming to the secondary cache interface of the microprocessor is embedded, the design cost in forming a secondary cache memory on a chip is expected to greatly reduce.
In, however, a conventional microprocessor using an off-chip type synchronous SRAM as a secondary cache memory, a strobe signal for instructing the start of a read/write cycle that is suitable for controlling the DRAM does not exist in various control signals for the secondary cache memory. For this reason, a dynamic semiconductor memory device used as the secondary cache memory of a microprocessor requires a means for detecting an address change in order to activate a word line and start the read/write cycle when an address input in the previous cycle is compared with an address input in the current cycle to detect an address change.
The performance of data exchange via the secondary cache interface of a microprocessor improves with increasing bit width. However, if the bit width is too large, the number of I/O pins increases to enlarge the package. To prevent this, the multi-bit width of the secondary cache of an existing microprocessor is divided into several parts. Further, a data latch for temporarily latching write/read data is arranged to serially transfer data in a burst mode, thereby suppressing an increase in the number of I/O pins.
Hence, a dynamic semiconductor memory device used as the secondary cache memory of a microprocessor must also be equipped with such data latch so as to enable burst data transfer of 2 bits or more.
The dynamic semiconductor memory device used as the secondary cache memory of a microprocessor must execute the read cycle for the same row address as that for the write cycle immediately after the end of the write cycle. However, a conventional DRAM does not have any means for detecting the end of the write cycle in advance. Although desired data has already been transferred to the data latch by burst data transfer operation, the data cannot be read out.
For this reason, e.g., the row address is changed to execute a dummy read cycle, and then the row address is returned to the original one to start the read cycle, thereby executing normal operation. In this case, since the dummy read cycle (2-clock cycle) is inserted, the effective data transfer rate decreases.
The present invention has been made in consideration of the above situation in the prior art, and has as the first object to provide a dynamic semiconductor memory device which has a data latch to enable burst data transfer of 2 bits or more, can detect an address change to active a word line and start the read/write cycle, and can detect a change from the write cycle to the read cycle to execute the read cycle for the same row address as that for the write cycle immediately after the end of the write cycle.
It is the second object of the present invention to provide a semiconductor memory device manufacturing method capable of reducing the design cost in forming a microprocessor and its secondary cache memory on a chip.
To achieve the first object, according to the first main aspect of the present invention, there is provided a dynamic semiconductor memory device for writing/reading out data in/from a memory cell via write/read means determined by a word line selected by a row address and a bit line selected by a column address, and temporally holding burst-written/read data by a data latch arranged on a data line connected to the write/read means, comprising address transition detection means for detecting an address change to generate an operation start instruction signal, and starting a write/read cycle in accordance with the operation start instruction signal, and read-after-write means for detecting a change from a write mode to a read mode to generate a read-after-write instruction signal, wherein when the read-after-write instruction signal is generated, data held by the write/read means is transferred to the data latch, and when the data is held by the data latch and read is done for the same row address, the data held by the data latch is read out and output.
The present invention comprises the following secondary aspects in addition to the first main aspect.
The address transition detection means comprises a plurality of address registers for holding a plurality of external row address signals, respectively, and an operation start instruction signal generation circuit for comparing row addresses in a previous write/read cycle with row addresses in a current write/read cycle in the plurality of address registers, and when the row addresses change as a result of comparison, generating the operation start instruction signal.
The read-after-write means comprises a write mode register for holding an external write mode signal, and an instruction signal generation circuit for outputting the read-after-write instruction signal when a signal obtained by delaying an output signal from the write mode register by one clock period changes from the write mode to the read mode.
The semiconductor memory device of the present invention is a secondary cache memory combined with a microprocessor.
The semiconductor memory device of the present invention may be mounted on the same chip as the microprocessor, or may be arranged outside a chip of the microprocessor.
To achieve the second object, according to the second main aspect of the present invention, there is provided a semiconductor memory device manufacturing method comprising the step of mounting, on one chip using a DRAM/logic embedding process, a layout macro of a microprocessor and a layout macro of a semiconductor memory device conforming to a secondary cache interface of the microprocessor.
As is apparent from the above aspects, in the arrangement of the present invention, a semiconductor memory device which comprises the data latch on a data line connected to the write/read means to burst-write/read out data detects an address change to generate an operation start instruction signal, and starts the write/read cycle in accordance with the operation start instruction signal. When the semiconductor memory device uses the secondary cache of a microprocessor in which a strobe signal for instructing the start of the read/write cycle that is suitable for controlling a DRAM does not exist in various control signals for the secondary cache interface, the word line can be activated to start the read/write cycle. At the same time, a change from the write mode to the read mode is detected to generate a read-after-write instruction signal, and data held by the write/read means is transferred to the data latch and latched in accordance with the read-after-write instruction signal. In performing read operation for the same row address, the held data is read out and output. Immediately after the write cycle, the read cycle for the same row address can be executed.
According to the semiconductor memory device manufacturing method of the present invention, the layout macro of a microprocessor and the layout macro of the semiconductor memory device according to the present invention conforming to the secondary cache interface of the microprocessor are embedded on one chip by a DRAM/logic embedding process. This can reduce the design cost in forming the secondary cache memory on a chip.
The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principle of the present invention are shown by way of illustrative examples.